| 摘要 |
A delay locked loop includes an auxiliary phase shifter for controlling a phase blending point after the delay locked loop is initially locked, thereby reducing jitter. A control circuit directs a phase blender to detect the point where two delayed signals are phase-blended, and directs the auxiliary phase shifter to select between a delayed clock signal and a received clock signal. When the point where the two delayed signals are phase-blended is in-between first edges of the two delayed signals, the control circuit directs the auxiliary phase shifter to transmit the received clock signal without delaying the clock signal. When the point where the two delayed signals are phase-blended is close to at least one of the first edges of the two delayed signals, the control circuit directs the auxiliary phase shifter to delay the clock signal by a predefined time. As a result, bang-bang jitter in the delay locked loop is reduced.
|
