MEMORY SYSTEM COMPRISING ECC BLOCK FOR REDUCING A LATENCY AND ERROR CORRECTION METHOD THEREOF

摘要

A memory system including an error correction block and an error correction method thereof are provided to enhance a speed of a read operation by performing error correction calculation at high speed when an error of a single-bit number is generated. A syndrome calculation block(110) calculates a syndrome of a read data. An error correction calculation block includes a single-bit error correction block(120) and a multi-bit error correction block(130). The single-bit error correction block calculates an error position by performing division calculation between elements of the syndrome. The multi-bit error correction block calculates an error position and an error pattern by performing a forward Chien search operation from the syndrome. An error correction circuit corrects an error of a read data with reference to the error position. A control part detects a single-bit error from the syndrome, and activates a single-bit error correction block.