发明名称 METHOD FOR CORROSION PREVENTION DURING PLANARIZATION
摘要 <p>The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eliminate Cu+ or Cu2+ migrations. In another aspect of the invention, a DC Voltage power supply is used to establish the negative bias.</p>
申请公布号 SG154373(A1) 申请公布日期 2009.08.28
申请号 SG20080089138 申请日期 2008.12.02
申请人 CHARTERED SEMICONDUCTOR MANUFACTURING LTD 发明人 FAN ZHANG;SAN LEONG LUP;KONG SIEW YONG;CHAO ZHANG BEI
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