发明名称 |
LATCH-UP FREE VERTICAL TVS DIODE ARRAY STRUCTURE USING TRENCH ISOLATION |
摘要 |
A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types. ® KIPO & WIPO 2009 |
申请公布号 |
KR20090091784(A) |
申请公布日期 |
2009.08.28 |
申请号 |
KR20097012853 |
申请日期 |
2007.11.30 |
申请人 |
ALPHA AND OMEGA SEMICONDUCTOR LIMITED |
发明人 |
BOBDE MADHUR |
分类号 |
H01L27/02;H01L29/861 |
主分类号 |
H01L27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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