| 摘要 |
An electronic circuitry based on current-mode logic is provided which comprise a logic unit (LP) having a plurality of latch logic units (L1, L2, LN) each with a hold node (H1 - HN) and a sample node (S1 - SN) and a clock unit (CP) having a sample node (S0) and a hold node (H0) as well as a clock circuitry (T1, T2, IN) for providing clock signals to the logic unit (LP) by providing clock controlled current to the latch logic units (L1 - LN). Each latch logic unit (L1, L2, LN) is coupled via their hold nodes (H1 - HN) and their sample nodes (S1 - SN) to the respective sample node (S0) and the hold node (H0) of the clock unit (CP). |
