| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To prevent the problem such as abort by surely interrupting access to an SDRAM in deep power down. <P>SOLUTION: A control port signal (13) for inhibiting the access to the SDRAM (3-2) controlled in the deep power down state is output from a control port (10) provided to a CPU (1). The control port signal (13) is input to an OR circuit (4) as a mask means together with a memory access control signal (12) from an SCRAM controller (2) for the SDRAM (3-2). When the SDRAM (3-2) is controlled in the deep power down state, the control port signal (13) is an H-level signal, and even when an L-level memory access control signal (12) is output from the SDRAM controller (2), a memory access control signal (14) output from the OR circuit (4) is masked by the H-level signal of the control port signal (13). <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
