SRAM MEMORY CELL BASED ON DOUBLE-GATE TRANSISTORS, PROVIDED WITH MEANS FOR IMPROVING THE WRITE MARGIN

摘要

Random-access memory cell, comprising: two double-gate access transistors (TA3L, TA3R) placed, respectively, between a first bit line (BLL) and a first storage node (L) and between a second bit line (BLR) and a second storage node (R); a word line (WL); a first double-gate charge transistor (TL1L) and a second double-gate charge transistor (TL1R); a first double-gate conduction transistor (TD1L) and a second double-gate conduction transistor (TD1R), the cell comprising: means for applying a given potential Vcell to at least one electrode of each of the charge or conduction transistors; and means for varying said given potential Vcell.