发明名称 |
DECODER CIRCUIT, DECODING METHOD, OUTPUT CIRCUIT, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC INSTRUMENT |
摘要 |
A decoder circuit comprises: first decoder section that decodes an m-bit address signal portion of an (m+n)-bit address signal; and a second decoder section that decodes an n-bit address signal portion of the (m+n)-bit address signal, the first decoder section including a first AND operation circuit section that outputs signals that indicate a decoding result of the m-bit address signal portion, and a second AND operation circuit section that outputs signals that indicate a decoding result of part of the m-bit address signal portion, and the second decoder section including a third AND operation circuit section that outputs signals that indicate a decoding result of the n-bit address signal portion, and a fourth AND operation circuit section that outputs signals that indicate a decoding result of part of the n-bit address signal portion.
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申请公布号 |
US2009212820(A1) |
申请公布日期 |
2009.08.27 |
申请号 |
US20090389938 |
申请日期 |
2009.02.20 |
申请人 |
SEIKO EPSON CORPORATION |
发明人 |
TORIUMI YUICHI;NISHIMURA MOTOAKI;NOMURA TAKESHI |
分类号 |
G11C8/10 |
主分类号 |
G11C8/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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