ARITHMETIC PROCESSING UNIT AND METHOD FOR CONTROLLING ARITHMETIC PROCESSING UNIT

摘要

A shared L2 cache section (102A) in a CPU (100a) serving as a multicore processor has a shared PFPORT (102j) shared by a plurality of CPU core sections(101) in addition to PFPORTs (102b) provided for every CPU core section(101). The shared PFPORT (102j) secures an entry upon the event of uncompleting of a prefetch request placed from the PFPORTs (102b) to an L2 pipeline processing section (102f). An uncompleted prefetch request is placed again from the shared PFPORT (102j) to the L2 pipeline processing section (102f).