发明名称
摘要 <P>PROBLEM TO BE SOLVED: To solve the problem that a potential of an output signal is reduced just for a potential drop caused by a through current when the through current is cased to flow while an input signal IN is at VSS level. <P>SOLUTION: A boot strap type inverter circuit 10 comprises an MOS transistor Qp14 for resetting a gate potential of an MOS transistor Qp12 to a VDD potential when a level of the input signal IN changes from the VDD potential to a VSS potential, and while the level of the input signal IN is the VSS potential, the MOS transistor Qp12 is completely turned off, so that the through current is not caused to flow. Furthermore, an MOS transistor Qp13 is provided for precharging the gate potential of the MOS transistor Qp12 to the VSS potential and when the level of the input signal IN is changed from a precharge state to the VDD potential, the MOS transistor Qp12 is completely turned on, so that the VSS potential is extracted as a level of an output signal OUT. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP4321266(B2) 申请公布日期 2009.08.26
申请号 JP20040002584 申请日期 2004.01.08
申请人 发明人
分类号 G02F1/133;H03K17/06;G09G3/20;G09G3/36;H01L21/8234;H01L27/08;H01L27/088;H01L29/786;H03K17/00;H03K17/16;H03K19/094 主分类号 G02F1/133
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