| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a delay circuit that generates a delay time which almost does not depend upon a power supply voltage and that easily prolongs the delay time, while suppressing an increase in current consumption and chip size. <P>SOLUTION: The delay circuit includes a current limit control circuit and a clocked inverter. The current limit control circuit includes a transistor P1 which is connected in series with a plurality of transistors between a first power supply potential and a node A, and a transistor N1 which is connected in series with a plurality of transistors between the node A and a second power supply potential, and in the current limit control circuit, an input signal is applied to a gate of the transistor P1 and a gate of the transistor N1. The clocked inverter includes transistors P2 and P3 connected in series between the first power supply potential and a node B, and transistors N2 and N3 connected in series between the node B and the second power supply potential. In the clocked inverter, an input signal is applied to gates of the transistors P2 and N2, and a signal is applied from the node A to gates of the transistors P3 and N3. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
