Memory Module Having Signal Lines Configured for Sequential Arrival of Signals at Synchronous Memory Devices

摘要

A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger. The first line segment and the second line segment are coupled together at a turn. A first synchronous memory device and a second synchronous memory device are coupled to the first line segment. The first signal arrives at the first synchronous memory device and the second synchronous memory device in a sequential manner. The memory module includes a clock line routed alongside the first signal line. A clock signal arrives at the first synchronous memory device and the second synchronous memory device in sequence alongside the first signal traversing along the first signal line.