| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a power semiconductor device having a low on-state voltage. <P>SOLUTION: In the power semiconductor device as an IEGT, a p-type collector layer 13, an n-type buffer layer 14 and a n-type base layer 15 are formed on a collector electrode in this order, and a main cell 21 and a dummy cell 22 are alternately provided on an upper surface of the n-type base layer 15 along a direction parallel to the n-type base layer 15. A trench gate electrode 18 is provided between the main cell 21 and the dummy cell 22. A p-type base layer 23 is provided in the main cell 21, and an n-type emitter layer 24 is disposed on a part of the upper surface of the p-type base layer. A p-type dummy layer 26 and an n-type dummy layer 27 are alternately formed along an extending direction of the trench gate electrode 18 in the dummy cell 22. <P>COPYRIGHT: (C)2009,JPO&INPIT |
