| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a mechanism for achieving both low standby current due to power shutdown and high-speed return from standby due to interruption. <P>SOLUTION: In an information processing device comprising a first area AE1 including a central processing unit CPU and peripheral circuit modules IP1 and IP2, a second area AE2 having information storage circuits URAM and BUREG for storing values of registers REG1 and 2 included in the peripheral circuit modules IP1 and IP2, and a first power source switch SW1 for controlling current supply to the first area AE1, when the information processing device operates in a first mode, operating current is supplied to the first area AE1 and the second area AE2, and when the information processing device operates in a second mode, the first power source switch SW1 is controlled so as to disconnect the current supply to the first area AE1, and the current supply to the second AE2 continues. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
