| 摘要 |
An integrated circuit has a hardware decoder that parses a frame to identify a type of encapsulation, such as Ethernet v2 encapsulation or 802.3 with or without one or more VLAN tags. The integrated circuit also has a number of hardware parsers, each parser being coupled to the decoder by an enable line. During packet processing, one of the parsers is enabled by the decoder, based on the value which identifies the encapsulation type. The enabled parser retrieves one or more attributes from the frame, depending on the encapsulation. The integrated circuit also has a register, coupled to each parser. The register holds the attributes retrieved by the parser. The integrated circuit also has a key generation hardware which creates a key, by concatenating from the attributes register, certain attributes that are pre-selected by a user for forming the key. The integrated circuit supplies the key to a memory (which may be either in the integrated circuit i.e. on-chip or outside the integrated circuit i.e. off-chip) to look up a set of user-specified actions to be performed on data in the frame. The actions may be specified by the user in the form of instructions to a processor.
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