| 摘要 |
PROBLEM TO BE SOLVED: To improve overall performance of a system including a semiconductor memory device such as a DRAM by supplying a front-loaded data read or write command. SOLUTION: A clock-synchronized memory is provided with an AL setting register 132 used for setting a value (front-loaded latency) specifying a supply cycle of a read or write command, and a delay control circuit 126 for delaying internal control signals MAE, WBE by the prescribed cycle time in accordance with a value set to the AL setting register 132. A read/write circuit 117 is controlled by delayed internal control signals MAE1, WBE1, thereby, read or write for a memory cell array is performed in timing in accordance with a value set to the AL setting register 132. Thereby, access to the memory cell array is made in correct timing. COPYRIGHT: (C)2009,JPO&INPIT
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