摘要 |
<p>An integrated circuit has a matrix of rows and columns of cells (10, 18, 19), each cell (10, 18, 19) comprising a first inverter (100) and a second inverter (102). First columns have a bit-line (12a,b), the first inverter inverter (100) and the second inverter (102) in each cell of the first columns being cross-coupled to each other and coupled to bit-line (12a,b) of the associated first column. A further column is provided in the matrix with bit line fragments (16) that are mutually disconnected. Delays are monitored by coupling at least the first inverters (100) of cells in respective pairs of rows in series via the bit-line fragments and measuring a delay during signal propagation through the series connection, for example by incorporating the series of inverters in a ring oscillator.</p> |
申请人 |
NXP B.V.;VEENDRICK, HENDRICUS, J., M.;BENTEN, HAROLD, G., P.;BARGAGLI-STOFFI, AGNESE, A., M.;VAN DE STEEG, PATRICK |
发明人 |
VEENDRICK, HENDRICUS, J., M.;BENTEN, HAROLD, G., P.;BARGAGLI-STOFFI, AGNESE, A., M.;VAN DE STEEG, PATRICK |