| 摘要 |
An electronic component of a Wafer Level Chip Scale Package (WLCSP) comprises an integrated device and a plurality of packaging layers in which routing between bond pad locations on the device (fig 1; 105) and solder ball lands 300 on the surface of the component in an under ball metallization layer (UBM) is provided by tracks 305 in an intermediate metallic redistribution layer (RDL) 310, 311. Vias allow electrical connection between the UBM and RDL layers, and the RDL and device bond pad layers. The RDL tracks may be routed below the extent of a solder ball land by providing a channel 304 through both the via 302, 303 and redistribution layer 310, 311 underneath the land. |
