发明名称
摘要 <p>In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A control circuit controls the potential on the word lines and bit lines according to the input data. The control circuit further controls the operations of writing data into, reading data from, and erasing data from the memory cells. A data storage circuit is connected to the bit lines and stores data under the control of the control circuit. The data storage circuit and the memory cell array are formed in the same well region.</p>
申请公布号 JP4316453(B2) 申请公布日期 2009.08.19
申请号 JP20040260033 申请日期 2004.09.07
申请人 发明人
分类号 H01L21/8247;G11C16/04;G11C16/06;H01L27/115;H01L29/788;H01L29/792 主分类号 H01L21/8247
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