发明名称 STACK PACKAGE
摘要 A stack package is provided to prevent degradation of an electrical performance by electrically connecting a bonding wire coated by an insulation material to a substrate. A cavity(C) is included in a center of a substrate(102). A first semiconductor chip(106) is attached on the cavity with a face down type. A first bonding wire(116) passes through the cavity, and connects the first semiconductor chip to the substrate. At least two or more second semiconductor chips(110,112,114) are attached on the first semiconductor chip with a face up type. A second bonding wire(118) connects the second semiconductor chip to the substrate. A surface of the second bonding wire is coated by an insulation material. The second semiconductor chip is formed with a center pad type or an edge pad type.
申请公布号 KR20090088272(A) 申请公布日期 2009.08.19
申请号 KR20080013702 申请日期 2008.02.14
申请人 HYNIX SEMICONDUCTOR INC. 发明人 JUNG, YOUNG BERM
分类号 H01L23/12;H01L23/48 主分类号 H01L23/12
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