| 摘要 |
A delay line of a DLL circuit is provided to perform a delay operation about a low frequency clock through unit delay parts of low number by setting a different delay time in a plurality of unit delay parts. A delay line of a DLL circuit includes a first delay part(10) and a second delay part(20). The first delay part includes a plurality of unit delay parts which is serially connected. The second delay part includes a plurality of unit delay parts which is serially connected, and is serially connected to the first delay part. A delay amount of the unit delay parts included in the first delay part is larger than a delay amount of the unit delay parts included in the second delay part. The first delay part receives a partial bit among delay control signals of multi-bit. The second delay part receives a rest bit among the delay control signals of multi-bit. |
