GATE PATTERNING SCHEME WITH SELF ALIGNED INDEPENDENT GATE ETCH
摘要
<p>A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.</p>
申请公布号
WO2009099987(A1)
申请公布日期
2009.08.13
申请号
WO2009US32800
申请日期
2009.02.02
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION;HALLE, SCOTT;COLBURN, MATTHEW, E.;DYER, THOMAS;DORIS, BRUCE
发明人
HALLE, SCOTT;COLBURN, MATTHEW, E.;DYER, THOMAS;DORIS, BRUCE