ARRANGEMENT FOR BICUBIC INTERPOLATION

摘要

The invention relates to a hardware structure for improving the efficiency of bicubic interpolation in connection with scaling of digital images in a device, such as a computer or a communication device, especially in a constrained embedded system where metrics such as memory usage, algorithm complexity, and power consumption needs to be closely monitored. The arrangement comprises a first computation unit (2), and a second computation unit (3), being adapted to output squares and cubes of offset values of a bicubic interpolation function. At least one interpolation block (5) is adapted to receive pixel values of a colour channel, and comprises a number of interpolation cores (4), each adapted to compute a reduced interpolation function based on pixel values and squares and cubes of offset values. The proposed architecture is scalable and minimizes computational and area cost.