| 摘要 |
Output circuit with reduced overshoot includes input end, output end, a circuit composed of PMOS and NMOS, rising and falling edge trigger bias circuits. The rising and falling edge trigger bias circuits output biasing voltages to the output end for clamping the voltage of the output signals respectively according to the rising edge and the falling edge of the input signal. In this way, the overshoot of the output signal is reduced.
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