| 摘要 |
A semiconductor memory device having a cell array area for reading or storing data, including: a normal cell block including a plurality of normal cells, each being coupled to one of a bit line and a bit line bar for storing a data; and a reference cell block including a plurality of reference cell units, each including a reference capacitor, a first reference transistor for connecting a first terminal of the reference capacitor to the bit line, a second reference transistor for connecting the first terminal of the reference capacitor to the bit line bar, and a third reference transistor connected to a reference voltage for supplying the reference voltage to the first terminal of the reference capacitor.
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