发明名称 Binary arithmetic decoding apparatus and methods using a pipelined structure
摘要 Binary arithmetic decoding methods and apparatus are provided. A first decoded bit and a first set of decoding parameters are generated using a previously generated set of decoding parameters. A second decoded bit and a second set of decoding parameters are generated using the first set of decoding parameters. If the first decoded bit is a last bit of a syntax element, the second set of decoding parameters is disregarded in generating subsequent decoded bits. The generation of the first and second decoded bits and determination of whether the first decoded bit is a last bit of a syntax element, e.g., a de-binarizing operation, may be pipelined such that the determination of whether the first decoded bit is a last bit of a syntax element occurs concurrent with and/or after generation of the second decoded bit and the second set of decoding parameters.
申请公布号 US7573951(B2) 申请公布日期 2009.08.11
申请号 US20050179137 申请日期 2005.07.12
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 KIM JI-HAK
分类号 H03K9/00;H04B14/04;H04L27/00 主分类号 H03K9/00
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