| 摘要 |
An image processing apparatus having an arithmetic circuit for generating pixel data of output pixels by arithmetically processing the pixel data of M horizontally adjoining pixels and N vertically adjoining pixels. A first temporary storage section readably stores the pixel data of the pixels ranging from the Mth pixel to the last pixel in each horizontal pixel line of an image. A second temporary storage section readably stores the pixel data of the pixels ranging from the head pixel to the (M-1)th pixel in each horizontal pixel line of the image. A third temporary storage section delays the pixel data stored in the first temporary storage section, receives the pixel data from the second temporary storage section, and simultaneously outputs pixel data of the M horizontally adjoining pixels and the N vertically adjoining pixels.
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