发明名称 |
Apparatus and methods for adjusting performance of integrated circuits |
摘要 |
A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
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申请公布号 |
US7573317(B2) |
申请公布日期 |
2009.08.11 |
申请号 |
US20060535065 |
申请日期 |
2006.09.26 |
申请人 |
ALTERA CORPORATION |
发明人 |
LEWIS DAVID;BETZ VAUGHN;RAHIM IRFAN;MCELHENY PETER;LIU YOW-JUANG W.;PEDERSEN BRUCE |
分类号 |
H03K3/01;G06F17/50;H03K5/00;H03K5/13;H03K19/00;H03K19/003 |
主分类号 |
H03K3/01 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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