| 摘要 |
FIELD: information technology. ^ SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic elements and executing arithmetic operations, particularly summation and subtraction, in positional-sign codes. Each bit of the adder contains four OR elements, two AND elements, three NOT elements and is made in form of two channels - a channel for generating positive sum and a channel for generating conditionally negative sum. ^ EFFECT: faster operation. ^ 5 dwg |
