| 摘要 |
A splitter having a counter embedded module is provided to improve the speed of processing image information. An image signal distributer(41) distributes image data transmitted from a camera to a PC. An FVAL signal checking unit(42) checks an FVAL signal which informs of the start and end of a scan line forming an image frame. A control circuit(43) controls the result transmitted from an input unit(44) and the timing of an FPGA signal.
|
