发明名称 |
EEPROM AND ELECTRONIC DEVICE USING IT |
摘要 |
<p><P>PROBLEM TO BE SOLVED: To shorten a writing time or reduce a circuit area. <P>SOLUTION: Memory cells MC are arranged in a matrix at crossing points of a plurality of bit lines BL and a plurality of word lines WL. Memory transistors MT have sources connected to the corresponding bit lines BL and have floating gates between control gates and conduction channels of drains and sources. Selection transistors ST have sources connected to the drains of the memory transistors MT and gates connected to the corresponding word lines WL. The source lines SL commonly join sources of some of the memory transistors MT in the plurality of memory cells MC. A charging circuit 40a charges the source lines SL. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
申请公布号 |
JP2009176366(A) |
申请公布日期 |
2009.08.06 |
申请号 |
JP20080014140 |
申请日期 |
2008.01.24 |
申请人 |
ROHM CO LTD |
发明人 |
OKUI AKIHIRO;NISHIYAMA HIDEKI |
分类号 |
G11C16/06;G11C16/02;G11C16/04 |
主分类号 |
G11C16/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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