发明名称 |
METHOD AND SYSTEM FOR VARACTOR LINEARIZATION |
摘要 |
Aspects of a method and system for varactor linearization are provided. In this regard, a relationship between control voltage and capacitance of a variable capacitor may be controlled utilizing a plurality of bias voltages communicatively coupled to a corresponding plurality of bias terminals of said variable capacitor. The variable capacitor may comprise a plurality of two-terminal unit varactors and a first terminal of each unit varactor may be coupled to an RF terminal of the variable capacitor, a second terminal of one of the unit varactors may be coupled to the control voltage, and a second terminal of each of the remaining unit varactors may be coupled to one of the bias voltages. The bias voltages may be generated via a resistor ladder and/or via the resistive nature of a portion of semiconductor substrate. The bias voltages may linearize the relationship between the control voltage and the capacitance.
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申请公布号 |
US2009195958(A1) |
申请公布日期 |
2009.08.06 |
申请号 |
US20080026661 |
申请日期 |
2008.02.06 |
申请人 |
VAVELIDIS KONSTANTINOS DIMITRIOS;GEORGANTAS THEODOROS;PLEVRIDIS SOFOKLIS EMMANOUEL |
发明人 |
VAVELIDIS KONSTANTINOS DIMITRIOS;GEORGANTAS THEODOROS;PLEVRIDIS SOFOKLIS EMMANOUEL |
分类号 |
H01G7/00 |
主分类号 |
H01G7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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