| 摘要 |
<p>To materialize a small planar dimension of an SRAM cell and stable operational margin in an E/R-type 4T-SRAM comprising vertical-type transistors SGT. In a static memory cell comprising four MOS transistors and two load resistance elements, the MOS transistors constituting the memory cell are formed on a planar silicon layer formed on an embedded oxide layer, the planar silicon layer being a storage node, and the MOS transistor having a structure in which a drain, a gate and a source are arranged in a vertical direction, with the gate surrounding a column-like semiconductor layer. Further, the load resistance element comprises a polysiliconplug formed on the planar silicon layer, thus materializing an SRAM cell with a small planar dimension.</p> |
