| 摘要 |
<p>Frequency of exclusion processing is reduced among a plurality of CPUs to improve processing performance when the plurality of CPUs carry out processing on a packet in parallel. To solve the problem, a processing sorting part (111) sorts processing of packets so that the packets received from the same connection are processed by the same parallel-processing CPU. A buffer assigning part (112) assigns a buffer region to be used in carrying out the processing for the parallel-processing CPU to which the processing is sorted. A FIFO monitor part (113) monitors FIFO parts (121-1 to 121-n) and detects whether or not there is a region available to be disengaged. A buffer disengaging part (114) disengages the buffer region when there is an available buffer region. The parallel-processing CPUs (120-1 to 120-n) register buffer position information of the buffer regions for storing unnecessary information in the FIFO parts (121-1 to 121-n).</p> |
