| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a multiprocessor system capable of achieving a barrier synchronization process of high efficiency. <P>SOLUTION: Processors CPU #0 to #7 each have a barrier write register BARW and a barrier read register BARR provided thereinside. Each BARW is connected to each BARR using a dedicated wiring block WBLK3. For example, the one-bit BARW of the CPU #0 is connected via the WBLK3 to the first bit of the eight-bit BARR included in each of the CPUs #0 to #7, and the one-bit BARW of the CPU #1 is connected via the WBLK3 to the second bit of the eight-bit BARR included in each of the CPUs #0 to #7. For example, the CPU #0 reports a wait for synchronization to the CPUs #1 to #7, by writing information in its own BARW, and recognizes whether or not the CPUs #1 to #7 are waiting for synchronization, by reading its own BARR. Thus, no special dedicated instructions are needed for a barrier synchronization process, and a process can be performed at high speed. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
