发明名称 Design Structure Of Implementing Power Savings During Addressing Of DRAM Architectures
摘要 A design structure embodied in a machine readable medium used in a design process includes random access memory device having an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Logic in signal communication with the array receives a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated.
申请公布号 US2009196118(A1) 申请公布日期 2009.08.06
申请号 US20080024443 申请日期 2008.02.01
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BARTLEY GERALD K.;BECKER DARRYL J.;BORKENHAGEN JOHN M.;GERMANN PHILIP R.;HOVIS WILLIAM P.
分类号 G11C8/00 主分类号 G11C8/00
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