| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an efficient DCT (discrete cosine transform) computing circuit of DCT-encoded data. <P>SOLUTION: An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations, and if disabled, is configured to transfer a second portion of processed data elements to at least one holding register. <P>COPYRIGHT: (C)2009,JPO&INPIT |
