BLOCK DECODING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE

摘要

A block decoding circuit of a semiconductor memory device is provided to generate a block selection signal normally reducing the mismatch between a delay unit and a repair address check circuit. In a block decoding circuit of a semiconductor memory device, a plurality of block decoders(B21~B24) decode a block select address. A plurality of repair address check circuits(R21-R24) check whether the block select address and word line select address are repair address or not. A dummy repair address check circuit(D21) produces a control signal by receiving the block select address and word line select address. A block selection signal generation circuit(21) outputs the output signals of a plurality of block decoders as block selection signals in response to the output signals of a plurality of repair address check circuits.