| 摘要 |
The present invention relates to a phase shift and synchronization control circuit (102) for interleaved PFC (Power Factor Correction) controllers. In order to control two separate PFC controllers (101; 102) working out of phase (at nearly 180 degrees) and with an appropriate duty-cycle, the circuit (103) comprises a first input terminal and a second input terminal, a first inverter (NOT1) and a second inverter (NOT2), a first data register (DFF1) and a second data register (DFF2), a first divider (DIV1) and a second divider (DIV2), an exclusive-OR gate (XOR), four NAND gates (AND1-AND4) and a first integrating network (D1, R1, C1) and a second integrating network (D2, R2, C2). The invention allows to correct the waveform of the line current to a sinusoid that is in phase with the line input voltage.
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