发明名称 |
Synchronization correction circuit for correcting the period of clock signals |
摘要 |
A transmission interval counter measures the period of a packet sync generated in a sync generator. A comparator compares the period of the packet sync to a reference interval as selected by a type selector to calculate a period error. A correction value calculator calculates a correction value based on the period error. An adder sums the correction value to a predetermined value to output a sum. A frequency dividing counter counts the high-speed clock signals to output its count, and is reset by a pulse. A comparator outputs the pulse when the count coincides with the sum. A circuit generates clocks synchronized with the pulses. A circuit frequency-divides the clocks by 1/8 to generate synchronization signals.
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申请公布号 |
US7570664(B2) |
申请公布日期 |
2009.08.04 |
申请号 |
US20020270608 |
申请日期 |
2002.10.16 |
申请人 |
OKI SEMICONDUCTOR CO., LTD. |
发明人 |
SHIMOSAKODA YOSHINORI |
分类号 |
H04J3/06;H04L7/08;G06F15/16;H04L7/00 |
主分类号 |
H04J3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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