| 摘要 |
A determination unit of a power-on reset circuit of a semiconductor integrated circuit is provided that ANDs (1) a first monitoring signal output from a first monitoring unit for monitoring when a first source voltage supplied from outside the semiconductor integrated circuit reaches a predetermined level and (2) a second monitoring signal output from a second monitoring unit for monitoring when an internal source voltage reaches a predetermined level, to produce a reset signal. In the determination unit, a first PMOS is inserted in series with a second PMOS connected between the first source voltage and a node. The conducting state of the second PMOS is controlled by the second monitoring signal. The conducting state of the first PMOS is controlled by the reset signal. Thus, even when the second monitoring signal becomes unstable and the second PMOS and a first NMOS are simultaneously turned on, the first PMOS is turned off, thus causing no flow of through current.
|
