发明名称 ARITHMETIC METHOD OF LAYOUT PATTERN, PHOTOMASK, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS
摘要 <p><P>PROBLEM TO BE SOLVED: To solve the problem that, when a contact layer positioned in another layer overlaps a narrow line&space pattern, that becomes a semi-transmissive pattern, disposed to remain a part of exposure light, for example, it is judged as disconnection electrically, so that, the contact region should be excluded as a rule violation, originally, namely, it is difficult to verify the contact region using a design rule checker. <P>SOLUTION: A region including a narrow line&space pattern is defined as a second region and the pattern and a normal pattern adjacent to the second region are handled as one aggregate pattern. When a mask including the second pattern is used, the intensity of light transmitted through second black and white regions is averaged and the light can be handled as a normal pattern for obtaining halftone light intensity. Therefore, processing can be performed using a rule checker such as DRC, LVS, ERC and the like, bugging is suppressed and the layout pattern can be obtained more accurately. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2009170832(A) 申请公布日期 2009.07.30
申请号 JP20080010100 申请日期 2008.01.21
申请人 SEIKO EPSON CORP 发明人 SERA HIROSHI
分类号 H01L21/82;G03F1/68;G03F1/70;G06F17/50;H01L21/336;H01L29/786 主分类号 H01L21/82
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