| 发明名称 |
Method and Process for Expediting the Return of Line Exclusivity to a Given Processor Through Enhanced Inter-node Communications |
| 摘要 |
Cache coherency latency is reduced through a method and apparatus that expedites the return of line exclusivity to a given processor in a multi-node data handling system through enhanced inter-node communications.
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| 申请公布号 |
US2009193192(A1) |
申请公布日期 |
2009.07.30 |
| 申请号 |
US20080021378 |
申请日期 |
2008.01.29 |
| 申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BURCKHARDT SEBASTIAN;O'NEILL ARTHUR J.;PAPAZOVA VESSELINA K.;WALTERS CRAIG R. |
| 分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
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