<p>A NAND flash memory device having a bit line and a plurality of storage cells coupled thereto. Programming circuitry is coupled to the plurality of storage cells concurrently to program two or more of the storage cells in different NAND strings associated with the same bit line.</p>
申请公布号
WO2009094298(A1)
申请公布日期
2009.07.30
申请号
WO2009US31191
申请日期
2009.01.16
申请人
RAMBUS INC.;KOYA, YOSHIHITO;BRONNER, GARY;WARE, FREDERICK, A.
