| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a receiver of a differential transfer system, which eliminates skew between clock data and skew between data. <P>SOLUTION: The receiver includes: a data latch signal generation circuit 12, which generates a data latch signal DCLKi (i=0 to the number of bits of unit data minus 1) for specifying latch timing of an internal data signal IND in synchronization with transition timing of the internal data signal IND outputted from a first differential input buffer 10; a data latch circuit 13, which generates an intermediate data signal LDi by latching the internal data signal IND at transition timing of the data latch signal DCLKi; an intermediate clock signal generation circuit 21, which generates an intermediate clock signal S[i:0] in synchronization with an internal clock signal INC outputted from a second differential input buffer 20; and a data signal regeneration circuit 14 that regenerates a received data signal RXD[i:0] by latching the intermediate data signal LDi with the intermediate clock signal S[i:0]. <P>COPYRIGHT: (C)2009,JPO&INPIT |
