| 摘要 |
SRAM includes reduced swing amplifiers, such that a first reduced swing amplifier serves as a local sense amp for reading a memory cell through a short local bit line, a second reduced swing amplifier serves as a segment sense amp for reading the local sense amp, and a third reduced swing amplifier serves as a global sense amp for reading the segment sense amp through a global bit line. When reading data, a voltage difference in the local bit line is converted to a time difference by the sense amps for differentiating low data and high data, which realizes low power consumption with the reduced swing amplifiers. And, lightly local bit line is quickly discharged when reading, which realizes fast operation. Furthermore, the local bit line is discharged by the reduced memory cell, which reduces area. Additionally, alternative circuits and memory cell structures for implementing the SRAM are described.
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