发明名称 PACKET PROCESSING DEVICE AND PACKET PROCESSING PROGRAM
摘要 <p>When a plurality of CPUs execute processing to packets in parallel, the frequency of the exclusive processing between the CPUs is reduced to improve the processing performance. A reception/distribution CPU (101) references a reception connection information table stored in a memory and distributes the packets to parallel processing CPUs (102-1 to 102-4) so that packets received from the same connection are received and processed by the same parallel processing CPU. The parallel processing CPUs (102-1 to 102-4) identify the input QoSs of the packets and notifies the input QoSs of the packets to QoS processing CPUs (103-1 to 103-4) corresponding to the identified input QoSs. The QoS processing CPUs (103-1 to 103-4) are provided correspondingly to a QoS processing queue group of the memory, respectively and execute the QoS processing to the corresponding QoS processing queue group.</p>
申请公布号 WO2009093299(A1) 申请公布日期 2009.07.30
申请号 WO2008JP50700 申请日期 2008.01.21
申请人 FUJITSU LIMITED;NAMIHIRA, DAISUKE 发明人 NAMIHIRA, DAISUKE
分类号 H04L12/54 主分类号 H04L12/54
代理机构 代理人
主权项
地址