发明名称 SAMPLE HOLD CIRCUIT, INTEGRATED CIRCUIT DEVICE, ELECTRO-OPTIC DEVICE, AND ELECTRONIC APPARATUS
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a sample hold circuit which can prevent the deterioration of characteristics of the circuit while reducing a circuit scale. <P>SOLUTION: A sample hold circuit comprises an operational amplifier OP1, a switch element SS for sampling, a capacitor for sampling, a switch element for feedback, and a switch element SA for flip-around. Sampling control lines LSP and LSN which supply sampling control signals for controlling the on/off-turning of the switch element SS for sampling are wired along the second direction D2 in the third direction D1 of a summing node line LNEG, and flip-around control lines LAP and LAN which supply flip-around control signals for controlling the on/off-turning of the switch element SA for flip-around are wired along the second direction D2 in the first direction D3 of a summing node line LNEG. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2009170483(A) 申请公布日期 2009.07.30
申请号 JP20080003907 申请日期 2008.01.11
申请人 SEIKO EPSON CORP 发明人 SHIN CHIHIRO;KIYA HIROSHI;KAMIJO HARUO;NISHIMURA MOTOAKI;MAKI KATSUHIKO
分类号 H01L21/822;G02F1/133;G09G3/20;G09G3/36;H01L21/8234;H01L27/04;H01L27/06;H01L27/088;H03K17/687 主分类号 H01L21/822
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