| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a DLL circuit that can generate a clock signal having an improved duty ratio characteristic and can more stably support operation of semiconductor integrated circuits, and to provide a method of controlling the same. <P>SOLUTION: A delay locked loop (DLL) circuit includes a clock signal dividing unit that can divide a reference clock signal by a prescribed division ratio and generate a division clock signal, a feedback loop that can perform a delay locked operation on the division clock signal and generate a delay clock signal, a half period delay unit that can delay the delay clock signal by a half period of the reference clock signal and generate a half period delay clock signal, and an operation unit that can combine the delay clock signal and the half period delay clock signal and generate an output clock signal. <P>COPYRIGHT: (C)2009,JPO&INPIT |
