发明名称 |
Phase Lock Loop Clock Distribution Method and System |
摘要 |
A method and apparatus and program use the quiet, regulated power supply inherent to the PLL to drive a CMOS buffer. In this manner, the CMOS buffer may distribute the reference clock in a manner that minimizes the power and space consumption associated with clock distribution processes.
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申请公布号 |
US2009189653(A1) |
申请公布日期 |
2009.07.30 |
申请号 |
US20080020794 |
申请日期 |
2008.01.28 |
申请人 |
FRIEND DAVID M;STROM JAMES D |
发明人 |
FRIEND DAVID M.;STROM JAMES D. |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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